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w982508bh 8m 4 banks 8 bit sdram publication release date: december 13, 2001 - 1 - revision a2 table of contents - 1. general descripti on ................................ ................................ ................................ .................. 3 2. features ................................ ................................ ................................ ................................ .......... 3 3. available pa rt number ................................ ................................ ................................ .............. 3 4. pin configuration ................................ ................................ ................................ ........................ 4 5. pin description ................................ ................................ ................................ ............................. 5 6. block diagram ................................ ................................ ................................ ............................... 6 7. electrical charac teristics ................................ ................................ ................................ .... 7 absolute maximum ratings ................................ ................................ ................................ ............... 7 recommended dc operating conditions ................................ ................................ ......................... 7 capacitance ................................ ................................ ................................ ................................ ....... 7 ac characteristics and operating condition ................................ ................................ ..................... 8 dc characteristics ................................ ................................ ................................ ............................. 9 8. operation mode ................................ ................................ ................................ .......................... 11 9. functional descri ption ................................ ................................ ................................ .......... 12 power - up and initialization ................................ ................................ ................................ ............... 12 programming mode register ................................ ................................ ................................ ........... 12 bank activate command ................................ ................................ ................................ ................. 12 read and write access modes ................................ ................................ ................................ ....... 12 burst read command ................................ ................................ ................................ ..................... 13 burst wr ite command ................................ ................................ ................................ ..................... 13 read interrupted by a read ................................ ................................ ................................ ............ 13 read interrupted by a write ................................ ................................ ................................ ............. 13 write interrupted by a write ................................ ................................ ................................ ............. 13 write interrupted by a read ................................ ................................ ................................ ............. 13 burst stop command ................................ ................................ ................................ ...................... 13 addressing sequence of sequential mode ................................ ................................ ..................... 14 addressing sequence of interleave mode ................................ ................................ ....................... 14 auto precha rge command ................................ ................................ ................................ .............. 15 precharge command ................................ ................................ ................................ ....................... 15 self refresh command ................................ ................................ ................................ ................... 15 powe r - down mode ................................ ................................ ................................ ........................... 15 no operation command ................................ ................................ ................................ .................. 16 deselect command ................................ ................................ ................................ ......................... 16 clock suspend mode ................................ ................................ ................................ ....................... 16
w982508bh - 2 - 10. timing waveforms ................................ ................................ ................................ .................... 17 command input timing ................................ ................................ ................................ ................... 17 read timing ................................ ................................ ................................ ................................ ..... 18 control timing of input/output data ................................ ................................ ................................ 19 mode register set cycle ................................ ................................ ................................ ................. 20 11. operating timing example ................................ ................................ ................................ .... 21 interleaved bank read (burst length = 4, cas latency = 3) ................................ ......................... 21 interleaved bank read (burst length = 4, cas latency = 3, auto precharge) .............................. 22 interleaved bank read (burst length = 8, cas latency = 3) ................................ ......................... 23 interle aved bank read (burst length = 8, cas latency = 3, auto precharge) .............................. 24 interleaved bank write (burst length = 8) ................................ ................................ ...................... 25 interleaved b ank write (burst length = 8, auto precharge) ................................ ........................... 26 page mode read (burst length = 4, cas latency = 3) ................................ ................................ . 27 page mode read/write (burs t length = 8, cas latency = 3) ................................ ........................ 28 auto precharge read (burst length = 4, cas latency = 3) ................................ ........................... 29 auto precharge write (burst length = 4) ................................ ................................ ........................ 30 auto refresh cycle ................................ ................................ ................................ .......................... 31 self refresh cycle ................................ ................................ ................................ ........................... 32 burst read a nd single write (burst length = 4, cas latency = 3) ................................ ................ 33 power - down mode ................................ ................................ ................................ ........................... 34 auto precharge timing (read cycle) ................................ ................................ .............................. 35 auto precharge timing (write cycle) ................................ ................................ .............................. 36 timing chart of read to write cycle ................................ ................................ ............................... 37 ti ming chart of write to read cycle ................................ ................................ ............................... 37 timing chart of burst stop cycle (burst stop command) ................................ .............................. 38 timing chart of burst stop cycle ( precharge command) ................................ .............................. 38 cke/dqm input timing (write cycle) ................................ ................................ ............................. 39 cke/dqm input timing (read cycle) ................................ ................................ ............................. 40 self refresh/power - down mode exit timing ................................ ................................ ................... 41 12. package dimensio n ................................ ................................ ................................ .................. 42 54l tsop (ii) - 400 mil ................................ ................................ ................................ ...................... 42
w982508bh publication release date: december 13, 2001 - 3 - revision a2 1. general descripti on w982508bh is a high - speed synchronous dynamic random access memory (sdram), organized as 8m words 4 banks 8 bits. using pipelined architecture and 0.175 m m process technology, w982508bh delivers a data bandwidth of up to 143m words per second ( - 7). to fully comply with the personal computer industrial standard, w982508bh is sorted into two speed grades: - 7 and - 75. the - 7 is compliant to the 143 mhz/cl3 or pc133/cl2 specification, the - 75 is compli ant to the pc133/cl3 specification, for handheld device application, we also provide a low power option, the 75l grade, with self refresh current under 1ma, and an industrial temperature option, the grade of 75i, which is guranteed to support - 40 c ? 85 c. accesses to the sdram are burst oriented. consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an active command. column addresses are automatically generated by the sdram internal counter in burst operation. random column read is also possible by providing its address at each clock cycle. the multiple bank nature enables interleaving among internal banks to hide the precharging time. by having a programmable mode register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. w982508bh is ideal for main memory in high performance applications. 2. features 3.3v 0.3v power supply up to 143 mhz clock frequency 8,38 8,608 words 4 banks 8 bits organization auto refresh and self refresh cas latency: 2 and 3 burst length: 1, 2, 4, 8, and full page burst read, single writes mode byte data controlled by dqm power - down mode auto precharge and controlled p recharge 8k refresh cycles / 64 ms interface: lvttl packaged in tsop ii 54 - pin, 400 mil - 0.80 3. available part nu mber part number speed grade self refresh current (max.) operating temperature w982508bh - 7 pc133/cl2 0 c ? 70 c w982508bh - 75 pc 133/cl3 3 ma 0 c ? 70 c w982508bh75l pc133/cl3 1 ma 0 c ? 70 c w982508bh75i pc133/cl3 1 ma - 40 c ? 85 c
w982508bh - 4 - 4. pin configuration v ss dq7 v ss q nc dq6 v cc q nc dq5 v ss q nc dq4 v cc q nc v ss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 v ss 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 v cc dq0 v cc q nc dq1 v ss q nc dq2 v cc q nc dq3 v ss q nc v cc nc bs0 bs1 a10/ap a0 a1 a2 a3 v cc cs ras cas we
w982508bh publication release date: december 13, 2001 - 5 - revision a2 5. pin description pin number pin name function description 23 - 26, 22, 29 - 36 a0 - a12 address multiplexed pins for ro w and column address. row address: a0 - a12. column address: a0 - a9. 20, 21 bs0, bs1 bank select select bank to activate during row address latch time, or bank to read/write during address latch time. 2, 5, 8, 11, 44, 47, 50, 53 dq0 - dq7 data input/ o utput multiplexed pins for data output and input. 19 cs chip select disable or enable the command decoder. when command decoder is disabled, new command is ignored and previous operation continues. 18 ras row addr ess strobe command input. when sampled at the rising edge of the clock, ras , cas and we define the operation to be executed. 17 cas column address strobe referred to ras 16 we write enable referred to ras 39 dqm input/output mask the output buffer is placed at hi - z(with latency of 2) when dqm is sampled high in read cycle. in write cycle, sampling dqm high will bl ock the write operation with zero latency. 38 clk clock inputs system clock used to sample inputs on the rising edge of clock. 37 cke clock enable cke controls the clock activation and deactivation. when cke is low, power - down mode, suspend mode, or self refresh mode is entered. 1, 14, 27 v cc power (+3.3v) power for input buffers and logic circuit inside dram. 28, 41, 54 v ss ground ground for input buffers and logic circuit inside dram. 3, 9, 43, 49 v cc q power (+3.3v) for i/o buffer separated power fro m v cc , to improve dq noise immunity. 6, 12, 46, 52 v ss q ground for i/o buffer separated ground from v ss , to improve dq noise immunity. 4, 7, 10, 13, 15, 40, 42, 45, 48, 51 nc no connection no connection
w982508bh - 6 - 6. block diagram dq0 dq7 dqm clk cke cs ras cas we a10 a0 a9 a11 a12 bs0 bs1 clock buffer command decoder address buffer refresh counter column counter control signal generator mode register column decoder sense amplifier cell array bank #2 column decoder sense amplifier cell array bank #0 column decoder sense amplifier cell array bank #3 data control circuit dq buffer column decoder sense amplifier cell array bank #1 note: the cell array configuration is 8192 * 1024 * 8. row decoder row decoder row decoder row decoder
w982508bh publication release date: december 13, 2001 - 7 - revision a2 7. electrical charac teristic s absolute maximum ratings parameter input, output voltage v in, v out - 0.3 - v cc +0.3 v 1 supply voltage v cc , v ccq - 0.3 - 4.6 v 1 operating temperature ( - 7/ - 75/75l) t opr 0 - 70 c 1 operating temperature (75i) t opr - 40 - 85 c 1 storage temperature t stg - 55 - 150 c 1 soldering temperature (10s) t solder 260 c 1 power dissipation p d 1 w 1 short circuit output current i out 50 ma 1 note: exposure to conditions beyond those listed under absolute maximum ratings may adversely aff ect the life and reliability of the device. recommended dc operating conditions (t a = 0 to 70 c for - 7/ - 75/75l, t a = - 40 to 85 c for 75i) parameter symbol min. typ. max. unit note supply voltage v cc 3.0 3.3 3.6 v 2 supply voltage (for i/o buffer) v cc q 3.0 3.3 3.6 v 2 input high voltage v ih 2.0 - v cc +0.3 v 2 input low voltage v il - 0.3 - 0.8 v 2 note: v ih (max . ) = v cc / v cc q+1.2v for pulse width < 5 ns v il (min . ) = v ss / v ss q - 1.2v for pulse width < 5 ns capacitance (v cc = 3.3v, f = 1 mhz, t a = 25 c) parameter symbol min. max. unit input capacitance (a0 to a12, bs0, bs1, cs , ras , cas , we , ldqm, udqm, cke) c i - 3.8 pf input capacitance (clk) c clk - 3.5 pf input/output capacitance c io - 6.5 pf note: these parameters are periodically sampled and not 100% tested.
w982508bh - 8 - ac characteristics and operating condition (vcc = 3.3v 0.3v, t a = 0 to 70 c for - 7/ - 75/75l, t a = - 40 to 85 c for 75i ; notes: 5, 6, 7, 8) parameter sym. - 7 (pc133, cl2) - 75/75l/75i (p c133, cl3) unit min. max. min. max. ref/active to ref/active command period t rc 56 65 active to precharge command period t ras 40 100000 45 100000 ns active to read/write command delay time t rcd 15 20 read/write(a) to read/write(b) command pe riod t ccd 1 1 cycle precharge to active command period t rp 15 20 active(a) to active(b) command period t rrd 15 15 write recovery time cl* = 2 t wr 7.5 10 cl* = 3 7 7.5 clk cycle time cl* = 2 t ck 7.5 1000 10 1000 cl* = 3 7 1000 7.5 1 000 clk high level width t ch 2.5 2.5 clk low level width t cl 2.5 2.5 access time from clk cl* = 2 t ac 5.4 6 cl* = 3 5.4 5.4 ns output data hold time t oh 3 3 output data high impedance time t hz 3 7 3 7.5 output data low impedance ti me t lz 0 0 power - down mode entry time t sb 0 7 0 7.5 transition time of clk (rise and fall) t t 0.5 10 0.5 10 data - in set - up time t ds 1.5 1.5 data - in hold time t dh 0.8 0.8 address set - up time t as 1.5 1.5 address hold time t ah 0.8 0.8 cke set - up time t cks 1.5 1.5 cke hold time t ckh 0.8 0.8 command set - up time t cms 1.5 1.5 command hold time t cms 0.8 0.8 refresh time t ref 64 64 ms mode register set cycle time t rsc 14 15 ns *cl = cas latency
w982508bh publication release date: december 13, 2001 - 9 - revision a2 dc characteristics (v cc = 3.3v 0.3v, t a = 0 to 70 c for - 7/ - 7575l, t a = - 40 to 85 c for 75i) parameter sym. - 7 (pc133, cl2) - 75/75l/75i (pc133, cl3) unit notes min. max. min. max. operating current t ck = min., t rc = min. active precharge command cycling without burst oper ation 1 bank operation i cc1 80 75 3 standby current t ck = min, cs = v ih cke = v ih i cc2 40 35 3 v ih / l = v ih (min.)/v il (max.) bank: inactive state cke = v il (power - down mode) i cc2p 1 1 3 standby current clk = v il , cs = v ih cke = v ih i cc2s 10 10 v ih / l = v ih (min.)/v il (max.) bank: inactive state cke = v il (power - down mode) i cc2ps 1 1 ma no operating current t ck = min., cs = v ih (min.) cke = v ih i cc3 60 55 bank: active state (4 banks) cke = v il (power - down mode) i cc3p 10 10 burst operating current t ck = min. read/ write command cycling i cc4 100 95 3, 4 auto refresh current t ck = min. auto refresh command cycling i cc5 170 160 3 standard ( - 7/ - 75) 3 3 self refresh current self refresh mode cke = 0.2v low power (75l/75i) i cc6l - 1 parameter sym. min. max. unit notes input leakage current (0v v in v cc , all other pins not under test = 0v) i i(l) - 5 5 m a output leakage current (output disable, 0v v out v ccq ) i o(l ) - 5 5 m a lvttl output " h " level voltage (i out = - 2 ma) v oh 2.4 - v lvttl output " l " level voltage (i out = 2 ma) v ol - 0.4 v
w982508bh - 10 - notes: 1. operation exceeds "absolute maximum rating" may cause permanent damage to the devices. 2. all voltages are referen ced to v ss 3. these parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of t ck and t rc . 4. these parameters depend on the output loading conditions. specified values are obtained with output open. 5. power - up sequence is further described in the "functional description" section. 6. ac testing conditions output reference level 1.4v/1.4v output load see diagram below input signal levels 2.4v/0.4v transition time (rise and fall) of input signal 2 ns i nput reference level 1.4v 50 ohms 1.4 v ac test load z = 50 ohms output 50pf 7. transition times are measured between v ih and v il . 8. t hz defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.
w982508bh publication release date: december 13, 2001 - 11 - revision a2 8. operation mode fully synchronous operations ar e performed to latch the commands at the positive edges of clk. table 1 shows the truth table for the operation commands. table 1 truth table (note (1) , (2)) command device state cken - 1 cken dqm bs0, 1 a10 a0 - a9 a11, a12 cs ras cas we bank active idle h x x v v v l l h h bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active (3) h x x v l v l h l l write with auto precharge active (3) h x x v h v l h l l read active (3) h x x v l v l h l h read with auto precharge active (3) h x x v h v l h l h mode register set idle h x x v v v l l l l no operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x auto refresh idle h h x x x x l l l h self refresh entry idle h l x x x x l l l h self refresh exit idle (s.r.) l l h h x x x x x x x x h l x h x h x x clock suspend mode entry active h l x x x x x x x x power - down mode entr y idle active (5) h h l l x x x x x x x x h l x h x h x x clock suspend mode exit active l h x x x x x x x x power - down mode exit any (power - down) l l h h x x x x x x x x h l x h x h x x data write/output enable active h x l x x x x x x x data write/o utput disable active h x h x x x x x x x notes: (1) v = valid x = don't care l = low level h = high level (2) cken signal is input level when commands are provided. cken - 1 signal is the input level one clock cycle before the command is issued. (3) these are state of bank designated by bs0, bs1 signals. (4) device state is full page burst operation. (5) power - down mode can not be entered in the burst cycle. when this command asserts in the burst cycle, device state is clock suspend mode.
w982508bh - 12 - 9. func tional description power - up and initialization the default power - up state of the mode register is unspecified. the following power - up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. during power - up, all vcc and vccq pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "nop" state. the power - up voltage must not exceed vcc +0.3v on any of the input pins or vcc supplies. after power - up, an i nitial pause of 200 m s is required followed by a precharge of all banks using the precharge command. to prevent data contention on the dq bus during power - up, it is required that the dqm and cke pins be held high during the initial pause period. once all b anks have been precharged, the mode register set command must be issued to initialize the mode register. an additional eight auto refresh cycles (cbr) are also required before or after programming the mode register to ensure proper subsequent operation. pr ogramming mode register after initial power - up, the mode register set command must be issued for proper device operation. all banks must be in a precharged state and cke must be high at least one cycle before the mode register set command can be issued. th e mode register set command is activated by the low signals of ras, cas, cs and we at the positive edge of the clock. the address input data during this cycle defines the parameters to be set as shown in the mode register operation table. a new command may be issued following the mode register set command once a delay equal to t rsc has elapsed. please refer to the next page for mode register set cycle and operation table. bank activate command the bank activate command must be applied before any read or wri te operation can be executed. the operation is similar to ras activate in edo dram. the delay from when the bank activate command is applied to when the first read or write operation can begin must not be less than the ras to cas delay time (t rcd ). once a bank has been activated it must be precharged before another bank activate command can be issued to the same bank. the minimum time interval between successive bank activate commands to the same bank is determined by the ras cycle time of the device (t rc ). the minimum time interval between interleaved bank activate commands (bank a to bank b and vice versa) is the bank to bank delay time (t rrd ). the maximum time that each bank can be held active is specified as t ras (max). read and write access modes after a bank has been activated , a read or write cycle can be followed. this is accomplished by setting ras high and cas low at the clock rising edge after minimum of t rcd delay. we pin voltage level defines whether the access cycle is a rea d operation (we high), or a write operation (we low). the address inputs determine the starting column address. reading or writing to a different row within an activated bank requires the bank be precharged and a new bank activate command be issued. when m ore than one bank is activated, interleaved bank read or write operations are possible. by using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pag es can be realized. read or write commands can also be issued to the same bank or between active banks on every clock cycle.
w982508bh publication release date: december 13, 2001 - 13 - revision a2 burst read command the burst read command is initiated by applying logic low level to cs and cas while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column address for the burst. the mode register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the mode register set up cycle. table 2 and 3 in the next page explain the address sequence of interleave mode and sequential mode. burst write command the burst write command is initiated by applying logic low level to cs, cas and we while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. data for the first burst write cycle must be applied on the dq pins on the same clock cycle that the write command is issued. the remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. data supplied to the dq pins after burst finishes will be ignored. read interrupted by a read a burst read may be interrupted by another read command. when the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. the data from the first read command continues to appear on the outputs until the cas latency from the interrupting read command the is satisfied. read interrupted by a write to interrupt a burst read with a write command, dqm may be needed to place the dqs (output drivers) in a high impedance state to avoid data contention on the dq bus. if a read command will issue data on the first and second clocks cycles of the write operation, dqm is needed to insure the dqs are tri - stated. after that point the write command will have control of the dq bus and dqm masking is no longer needed. write interrupted by a write a burst write may be interrupted before completion of the burst by another write c ommand. when the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. write interrupted by a read a read command will interrupt a burst write operation on the same clock cycle that the read command is activated. the dqs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. when the read command is activated, a ny residual data from the burst write cycle will be ignored. burst stop command a burst stop command may be used to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank, if th e burst length is full page. use of the burst stop command during other burst length operations is illegal. the burst stop command is defined by having ras and cas high with cs and we low at the rising edge of the clock.
w982508bh - 14 - the data dqs go to a high impedance state after a delay which is equal to the cas latency in a burst read cycle interrupted by burst stop. if a burst stop command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored. addressin g sequence of sequential mode a column access is performed by increasing the address from the column address which is input to the device. the disturb address is varied by the burst length as shown in table 2 . table 2 address sequence of sequential mode da ta access address burst length data 0 n bl = 2 (disturb address is a0) data 1 n + 1 no address carry from a0 to a1 data 2 n + 2 bl = 4 (disturb addresses are a0 and a1) data 3 n + 3 no address carry from a1 to a2 data 4 n + 4 data 5 n + 5 bl = 8 (disturb addresses are a0, a1 and a2) data 6 n + 6 no address carry from a2 to a3 data 7 n + 7 addressing sequence of interleave mode a column access is started in the input column address and is performed by inverting the address bit in the sequence shown in table 3. table 3 address sequence of interleave mode data access address bust length data 0 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 2 data 1 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 2 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 4 da ta 3 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 4 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 8 data 5 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 6 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 7 a8 a7 a6 a5 a4 a3 a2 a1 a0
w982508bh publication release date: december 13, 2001 - 15 - revision a2 auto precharge command if a10 is set to high when the read or write command is issued, then the auto precharge function is entered. during auto pr echarge, a read command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. the number of clocks is determined by cas latency. a read or write command with auto precharge can not be interrupted before the entire burst operation is completed. therefore, use of a read, write, or precharge command is prohibited during a read or write cycle with auto precharge. once the precharge operation has started, the bank cannot be reactivated until the precharge time (t rp ) has been satisfied. issue of auto precharge command is illegal if the burst is set to fu ll page length. if a10 is high when a write command is issued, the write with auto precharge function is initiated. the sdram automatically enters the precharge operation one clock delay from the last burst write cycle. this delay is referred to as write t wr . the bank undergoing auto precharge can not be reactivated until t wr and t rp are satisfied. this is referred to as t dal , data - in to active delay (t dal = t wr + t rp ). when using the auto precharge command, the interval between the bank activate command an d the beginning of the internal precharge operation must satisfy t ras (min). precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is entered when cs, ras and we are low and cas is high at the rising edge of the clock. the precharge command can be used to precharge each bank separately or all banks simultaneously. three address bits, a10, bs0, and bs1, are used to define which bank(s) is to be precharged when the command is issued. after the precharge command is issued, the precharged bank must be reactivated before a new read or write access can be executed. the delay between the precharge command and the activate command must be greater than or equal to the precharge time (t rp ). self ref resh command the self refresh command is defined by having cs, ras, cas and cke held low with we high at the rising edge of the clock. all banks must be idle prior to issuing the self refresh command. once the command is registered, cke must be held low t o keep the device in self refresh mode. when the sdram has entered self refresh mode all of the external control signals, except cke, are disabled. the clock is internally disabled during self refresh operation to save power. the device will exit self refr esh operation after cke is returned high. a minimum delay time is required when the device exits self refresh operation and before the next command can be issued. this delay is equal to the t ac cycle time plus the self refresh exit time. if, during normal operation, auto refresh cycles are issued in bursts (as opposed to being evenly distributed), a burst of 8,192 auto refresh cycles should be completed just prior to entering and just after exiting the self refresh mode. power - down mode the power - down mode is initiated by holding cke low. all of the receiver circuits except cke are gated off to reduce the power. the power - down mode does not perform any refresh operations, therefore the device can not remain in power - down mode longer than the refresh period (t ref ) of the device.
w982508bh - 16 - the power - down mode is exited by bringing cke high. when cke goes high, a no operation command is required on the next rising clock edge, depending on t ck . the input buffers need to be enabled with cke held high for a period equal to t cks (min) + t ck (min). no operation command the no operation command should be used in cases when the sdram is in a idle or a wait state to prevent the sdram from registering any unwanted commands between operations. a no operation command is registere d when cs is low with ras, cas, and we held high at the rising edge of the clock. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. deselect command the deselect command performs t he same function as a no operation command. deselect command occurs when cs is brought high, the ras, cas, and we signals become don't cares. clock suspend mode during normal access mode, cke must be held high enabling the clock. when cke is registered l ow while at least one of the banks is active, clock suspend mode is entered. the clock suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. there is a one clock delay between the registration of cke low and the time at which the sdram operation suspends. while in clock suspend mode, the sdram ignores any new commands that are issued. the clock suspend mode is exited by bringing cke high. there is a one clock cycle delay from when cke returns high to when clock suspend mode is exited.
w982508bh publication release date: december 13, 2001 - 17 - revision a2 10. timing waveforms command input timing clk a0-a12 bs0, 1 v ih v il t cmh t cms t ch t cl t t t t t cks t ckh t ckh t cks t cks t ckh command input timing cs ras cas we cke t cms t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah t ck
w982508bh - 18 - timing waveforms, continued read timing read cas latency t ac t lz t ac t oh t hz t oh burst length read command clk cs ras cas we a0 - a12 bs0, 1 dq valid data-out valid data-out
w982508bh publication release date: december 13, 2001 - 19 - revision a2 timing waveforms, continued control timing of input/output data t cmh t cms t cmh t cms t ds t dh t ds t dh t ds t dh t ds t dh valid data-out valid data-out valid data-out valid data-in valid data-in valid data-in valid data-in t ckh t cks t ckh t cks t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in t cmh t cms t cmh t cms t oh t ac t oh t ac t oh t hz open t lz t ac t oh t ac t ckh t cks t ckh t cks t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out clk dqm dq0 -7 (word mask) (clock mask) clk cke dq0 -7 clk input data output data (output enable) (clock mask) dqm dq0 -7 cke clk dq0 -7
w982508bh - 20 - timing waveforms, continued mode register set cycle a0 a1 a2 a3 a4 a5 a6 burst length addressing mode cas latency (test mode) a8 reserved a0 a7 a0 a9 a0 write mode a10 a12 a0 a11 a0 bs0 "0" "0" a0 a3 a0 addressing mode a0 0 a0 sequential a0 1 a0 interleave a0 a9 single write mode a0 0 a0 burst read and burst write a0 1 a0 burst read and single write a0 a0 a2 a1 a0 a0 0 0 0 a0 0 0 1 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 1 0 1 a0 1 1 0 a0 1 1 1 a0 burst length a0 sequential a0 interleave 1 a0 1 a0 2 a0 2 a0 4 a0 4 a0 8 a0 8 a0 reserved a0 reserved a0 full page a0 cas latency a0 reserved a0 reserved 2 a0 3 reserved a0 a6 a5 a4 a0 0 0 0 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 0 0 1 t rsc t cms t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah clk cs ras cas a0-a12 bs0,1 register set data next command a0 reserved "0" "0" "0" "0" we a0 bs1 "0"
w982508bh publication release date: december 13, 2001 - 21 - revision a2 11. operating timing example interleaved bank read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9, a11,12 a10 bs1 we cas ras cs bs0 t rc t rc t rc t rc t ras t rp t ras t rp t rp t ras t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read precharge precharge precharge raa rbb rac rbd rae raa caw rbb cbx rac cay rbd cbz rae aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 bank #0 idle bank #1 bank #2 bank #3
w982508bh - 22 - operating timing example, continued interleaved bank read (burst length = 4, cas latency = 3, auto precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk cke dqm a0-a9, a11,12 a10 bs1 we cas ras cs bs0 t rc t rc t rc t ras t rp t ras t rp t ras t rp t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read t rc raa rbb rac rbd rae dq aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dz0 * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 ap* ap* ap* raa caw rbb cbx rac cay rbd rae cbz
w982508bh publication release date: december 13, 2001 - 23 - revision a2 operating timing example, continued interleaved b ank read (burst length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t rc t rc t ras t rp t ras t rp t ras t rp t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 cz0 (clk = 100 mhz) clk dq cke dqm a0-a9, a11,12 a10 bs0 we cas ras cs bs1 active read precharge active read precharge active t ac t ac read precharge t ac bank #0 idle bank #1 bank #2 bank #3
w982508bh - 24 - operating timing example, continued interleaved bank read (burst length = 8, cas latency = 3, auto precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t rc t ras t rp t ras t ras t rp t rcd t rcd t rcd t rrd t rrd ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 cz0 raa raa cax rbb rbb cby (clk = 100 mhz) rac rac caz * ap is the internal precharge start timing active read active active read t cac t cac t cac clk dq cke dqm a0-a9, a11,12 a10 bs1 we cas ras cs bank #0 idle bank #1 bank #2 bank #3 read ap* ap* bs0
w982508bh publication release date: december 13, 2001 - 25 - revision a2 operating timing example, continued interleaved bank write (burst length = 8) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rp t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 (clk = 100 mhz) write precharge active active write precharge active write clk dq cke dqm a0-a9, a11,12 a10 bs0 we cas ras cs bs1 idle bank #0 bank #1 bank #2 bank #3 t ras
w982508bh - 26 - operating timing example, continued interleaved bank write (burst length = 8, auto precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t ras t rp t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rab rac ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 caz (clk = 100 mhz) * ap is the internal precharge start timing clk dq cke dqm a0-a9, a11,12 a10 bs0 we cas ras cs bs1 active write write active bank #0 idle bank #1 bank #2 bank #3 ap* active write ap*
w982508bh publication release date: december 13, 2001 - 27 - revision a2 operating timing example, continued page mode read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ccd t ccd t ccd t ras t rp t ras t rp t rcd t rcd t rrd raa raa cai rbb rbb cbx cay cam cbz a0 a1 a2 a3 bx0 bx1 ay0 ay1 ay2 am0 am1 am2 bz0 bz1 bz2 bz3 (clk = 100 mhz) * ap is the internal precharge start timing clk dq cke dqm a0-a9, a11,12 a10 bs0 we cas ras cs bs1 active read active read read read read precharge t ac t ac t ac t ac t ac bank #0 idle bank #1 bank #2 bank #3 ap*
w982508bh - 28 - operating timing example, continued page mode read/write (burst length = 8, c as latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ras t rp t rcd t wr raa raa cax cay ax0 ax1 ax2 ax3 ax4 ax5 ay1 ay0 ay2 ay4 ay3 q q q q q q d d d d d (clk = 100 mhz) clk dq cke dqm a0-a9, a11,12 a10 bs0 we cas ras cs bs1 active read write precharge t ac bank #0 idle bank #1 bank #2 bank #3
w982508bh publication release date: december 13, 2001 - 29 - revision a2 operating timing example, continued auto precharge read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9, a11,12 a10 bs1 we cas ras cs bs0 t rc t rc t ras t rp t ras t rp t rcd t rcd t ac active read ap* active read ap* raa rab raa caw rab cax aw0 aw1 aw2 aw3 * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 t ac bx0 bx1 bx2 bx3
w982508bh - 30 - operating timing example, continued auto precharge write (burst length = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9, a11,12 a10 bs1 we cas ras cs bs0 t rc t rc t ras t rp t ras t rp raa t rcd t rcd rab rac raa caw rab cax rac aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 active active write ap* active write ap* * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3
w982508bh publication release date: december 13, 2001 - 31 - revision a2 operating timing example, continued auto refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) all banks prechage auto refresh auto refresh (arbitrary cycle) t rc t rp t rc clk dq cke dqm a0-a9, a11,12 a10 we cas ras cs bs0,1
w982508bh - 32 - o perating timing example, continued self refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9, a11,12 a10 bs0,1 we cas ras cs t cks t sb t cks t cks all banks precharge self refresh entry arbitrary cycle t rp self refresh cycle t rc no operation cycle
w982508bh publication release date: december 13, 2001 - 33 - revision a2 operating timing example, continued burst read and single write (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk cs ras cas we bs0 bs1 a10 a0-a9, a11,12 dqm cke dq (clk = 100 mhz) t rcd rba rba cbv cbw cbx cby cbz av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3 q q q q d d d q q q q t ac t ac read read single write active bank #0 idle bank #1 bank #2 bank #3
w982508bh - 34 - operating timing example, continued power - down mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) raa caa raa cax raa raa ax0 ax1 ax2 ax3 t sb t cks t cks t cks t sb t cks active standby power down mode precharge standby power down mode active nop precharge nop active note: the powerdown mode is entered by asserting cke "low". all input/output buffers (except cke buffers) are turned off in the powerdown mode. when cke goes high, command input must be no operation at next clk rising edge. clk dq cke dqm a0-a9 a11,12 a10 bs we cas ras cs read
w982508bh publication release date: december 13, 2001 - 35 - revision a2 operating timing example, continued au to precharge timing (read cycle) read ap 0 11 10 9 8 7 6 5 4 3 2 1 q0 q0 read ap act q1 read ap act q1 q2 ap act read act q0 q3 (1) cas latency=2 read act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least t ras (min). represents the read with auto precharge command. represents the start of internal precharging. represents the bank activate command. note ) t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq q0 q1 q2 q3 q4 q5 q6 q7 t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq q0 read ap act q0 read ap act q1 q0 read ap act q1 q2 q3 read ap act q0 q1 q2 q3 q4 q5 q6 q7 (2) cas latency=3 t rp t rp t rp t rp
w982508bh - 36 - operating timing example, continued auto precharge timing (write cycle) write act ap 0 11 10 9 8 7 6 5 4 3 2 1 d0 d0 d0 d0 ap act d1 ap act d1 d1 d2 d2 d3 d3 d4 d5 d6 d7 ap act write write write (1) cas latency=2 write act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least tras (min). represents the write with auto precharge command. represents the start of internal precharging. represents the bank activate command. note ) t rp t wr t rp t wr t rp t wr t rp t wr ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq d0 ap act ap act d1 d0 ap act d1 d2 d3 ap act d0 d1 d2 d3 d4 d5 d6 d7 write write write write d0 (2) cas latency=3 t rp t wr t rp t wr t rp t wr t rp t wr ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq
w982508bh publication release date: december 13, 2001 - 37 - revision a2 operating timing example, continued timing chart of read to write cycle note: the output data must be masked by dqm to avoid i/o conflict 11 10 9 8 7 6 5 4 3 2 1 0 (1) cas latency=2 in the case of burst length = 4 read read write write dq dq ( b ) command dqm dqm d0 d1 d2 d3 d0 d1 d2 d3 ( a ) command (2) cas latency=3 read write read write d0 d1 d2 d3 ( a ) command dq dq dqm ( b ) command dqm d0 d1 d2 d3 timing chart of write to read cycle read write 0 11 10 9 8 7 6 5 4 3 2 1 q0 read q1 q2 q3 read read write write q0 q1 q2 q3 write q0 q1 q2 q3 d0 d1 dq dq ( a ) command dq dq dqm ( b ) command dqm ( a ) command ( b ) command dqm dqm in the case of burst length=4 (1) cas latency=2 (2) cas latency=3 d0 d0 d1 q0 q1 q2 q3 d0
w982508bh - 38 - operating timing example, co ntinued timing chart of burst stop cycle (burst stop command) read bst 0 11 10 9 8 7 6 5 4 3 2 1 dq q0 q1 q2 q3 bst ( a ) cas latency =2 command ( b )cas latency = 3 (1) read cycle q4 (2) write cycle command read command q0 q1 q2 q3 q4 q0 q1 q2 q3 q4 dq dq write bst note: represents the burst stop command bst timing chart of burst stop cycle (precharge command) in the case of burst lenght = 8 read prcg 0 11 10 9 8 7 6 5 4 3 2 1 q0 q1 q2 q3 q0 q1 q2 q3 read prcg q4 q4 ( a )cas latency =2 command ( b )cas latency = 3 command dq dq dq ( b )cas latency = 3 command (1) read cycle (2) write cycle write write prcg prcg ( a ) cas latency =2 command dqm dqm t wr t wr d0 d1 d2 d3 d4 dq d0 d1 d2 d3 d4 dq
w982508bh publication release date: december 13, 2001 - 39 - revision a2 operating timing example, continued cke/dqm input timing (write cycle) 7 6 5 4 3 2 1 cke mask ( 1 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 2 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 3 ) d1 d6 d5 d4 d3 d2 clk cycle no. external cke dqm dq dqm mask dqm mask cke mask cke mask internal clk clk clk
w982508bh - 40 - operating timing example, continued cke/dqm input timing ( read cycle) 7 6 5 4 3 2 1 ( 1 ) q 1 q 6 q 4 q 3 q 2 clk cycle no. external internal cke dqm dq open open 7 6 5 4 3 2 1 q 1 q 6 q 3 q 2 clk cycle no. external internal cke dqm dq open ( 2 ) 7 6 5 4 3 2 1 q 1 q 6 q 3 q 2 clk cycle no. external internal cke dqm dq q 5 q 4 ( 3 ) q 4 clk clk clk
w982508bh publication release date: december 13, 2001 - 41 - revision a2 operating timing example, continued self refresh/power - down mode exit timing asynchronous control input buffer turn on time ( power down mode exit time ) is specified by tcks(min) + tck(min) command nop clk cke command a ) t ck < t cks (min)+t ck (min) input buffer enable command clk cke command b) t ck >= t cks (min) + t ck (min) input buffer enable note ) command nop all input buffer(include clk buffer) are turned off in the power down mode and self refresh mode represents the no-operation command represents one command t ck t ck t cks (min) +t ck (min) t cks (min) +t ck (min)
w982508bh - 42 - 12. package dimensio n 54l tsop (ii) - 400 mil seating plane e d a2 a1 a e b zd 1 27 54 28 h e y l c l1 zd 0.71 0.028 0.002 0.009 max. min. nom. a2 b a a1 0.24 1.00 0.05 0.40 1.20 0.15 sym. dimension (mm) max. min. nom. e 0.80 0.0315 0.016 l 0.40 0.50 0.60 0.020 0.024 0.396 e 10.06 10.16 10.26 0.400 0.404 0.871 d 22.22 22.12 22.62 0.875 0.905 0.039 0.016 0.047 0.006 dimension (inch) 0.10 0.004 0.32 l1 0.80 0.032 c 0.15 0.006 0.012 0.455 11.76 11.56 11.96 0.463 0.471 h e y 0.10 0.004 controlling dimension: millimeters
w982508bh publication release date: december 13, 2001 - 43 - revision a2 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office 11f, no. 115, sec. 3, taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 min-sheng east. rd.,

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